As semiconductor integrated circuit chips become more multi-functional and highly integrated, the chips include more bonding pads (or terminal pads), and thus packages for the chips have more external terminals (or leads). When a conventional plastic package having leads along the perimeter of the package must accommodate a large number of leads, the footprint of the package increases.
However, a goal in many electronic systems is to minimize an overall size of the systems. Thus, to accommodate a large number of pins without increasing the footprint of package, pin pitch (or lead pitch) of the package must decrease. However, a pin pitch of less than about 0.4 mm gives rise to many technical concerns. For example, trimming of a package having a pin pitch less than 0.4 mm requires expensive trimming tools. Furthermore, the leads are prone to bending during handling of the package. In addition, surface-mounting of such packages demands a costly and complicated surface-mounting process due to a required critical alignment step.
Thus, to avoid technical problems associated with conventional fine-pitch packages, packages having area array external terminals have been suggested, such as a ball grid array package or chip scale package (e.g., micro ball grid array package (μBGA) and a bump chip carrier (BCC)). A μBGA package includes a polyimide tape on which a conductive pattern is formed. Such a package employs a different manufacturing process as compared to conventional plastic packaging. The BCC, on the other hand, includes a substrate having grooves formed around a central portion of a top surface of a copper alloy plate, and an electroplating layer formed in the grooves. Accordingly, chip scale packages utilize specialized packaging materials and processes which increase package manufacturing costs.
An integrated circuit package using conventional packaging materials and processes can only be accessed for electrical interconnection, for example, to a printed circuit board, by the bump pads on the bottom surface 121 of the package. See, for example, FIGS. 1A through 1C, which illustrate plan and cross-sectional views of a conventional apparatus for manufacturing leadless BCC packages.
With reference to the plan view of FIG. 1A, a conventional metal carrier matrix array 101 has an upper surface 103, which includes an encapsulating matrix 105 with a plurality of sawing lines 107.
The cross-sectional view of FIG. 1B shows a plurality of bump pads 109 and a plurality of die pads 111 formed on the upper surface 103 of the metal carrier 101 by plating. Back surfaces of integrated circuit dice 113 are attached to corresponding die pads 111. A plurality of bonding wires 115 connect a plurality of bonding pads 117 on active surfaces of the dice 113 to corresponding bump pads 109. An encapsulant 119 encapsulates the encapsulating matrix 105, including the dice 113 and the bonding wires 115.
With reference to the underside plan view of FIG. 1C, after etching away the metal carrier 101 (not shown in FIG. 1C), the bump pads 109 and the die pads 111 are exposed from the bottom surface 121 of the encapsulant 119. Thereafter, the encapsulant 119 is singulated by sawing along the sawing lines 107 to form a plurality of individual BCC packages.